1. Field of the Invention
This invention relates to a time delay circuit used in a semiconductor device, and particularly to a circuit used to reduce malfunctions caused by noise as used well as to speed up the semiconductor device.
2. Description of the Related Art
A time delay circuit, which has been used in semiconductor devices, produces an output signal S.sub.o at a predetermined delay time t.sub.1 measured after an application of an input signal S.sub.i on its input terminal. Among some types of time delay circuits, there is a CR (Capacitance, Resistance) type, in which the input signal S.sub.i is applied via a resistor R to a capacitor C. A voltage V.sub.c slowly produced on the capacitor C is detected by a logical gate circuit G at a predetermined threshold level V.sub.th for outputting delayed signals S.sub.o, as shown in FIG. 1 and FIGS. 2A-2D using positive pulses. In this type of circuit, if a noise pulse, N.sub.1 etc., which is usually short, is input to the time delay circuit 1, the noise pulse charges the time delay circuit 1. Before the charge is completely discharged, if an input signal pulse S.sub.i is input, the voltage V.sub.c on the capacitor C rises to the threshold level V.sub.th after a period T.sub.2 which is shorter than the normal delay period T.sub.1, resulting in malfunction of the time delay circuit, as shown in FIGS. 3A-3C. These kind of noise pulses are very possible for the delay circuit 1 in a semiconductor device. On the other hand, this type of delay circuit can not accept the next input signal until the charge in the delay circuit is completely discharged, for the same reason the voltage V.sub.c of the capacitor rises and reaches the threshold level V.sub.th earlier than the normal delay period T.sub.1. Thus a malfunction results. In order to solve this problem, there may be provided a circuit which compulsively discharges the residual charge in the capacitor as soon as the delayed signal is output.
However, this measure is not effective for some types of CR delay circuits, such as a distributed CR delay circuit, i.e., a dummy word line which is made similar to a word line of a semiconductor memory device. The word line of a semiconductor IC memory is generally made of relatively high electrically resistive material, such as polycrystalline silicon. Further, the word line has a relatively large stray capacitance along each line. Thus, the word line, i.e., the dummy word line, forms a distributed CR delay circuit. The distributed delay circuit takes some time not only to charge up the capacitances but also to discharge the capacitances, so that the compulsive discharging is not effective for the distributed CR delay circuit. The larger the scale of integration is attempted, the finer, i.e., the more resistive, the word line becomes thus requiring more time to charge and discharge. Also, the higher the cycle speed required in a memory device, the more serious this problem becomes. Therefore, an improved delay circuit which is less susceptive to noise inputs and which is quicker to be ready to accept the next input signal after completion of a delaying operation, has been requested.